1. Field of the Invention
The present invention generally relates to the testing of data processors having memory and, more particularly, to the execution of built-in tests (BIT) of memory in single board computers.
2. Description of the Prior Art
Many systems are currently in use which require the inclusion of many data processors to provide the complex control functions which may be required. Avionics is exemplary of fields in which such complex control systems are often required to gather information about the aircraft condition, attitude (e.g. roll, pitch, yaw) and environment (e.g. altitude, temperature) and to control flight surfaces and other aircraft mechanisms to achieve the operations that the pilot may desire.
In such applications, the data processors are generally provided in the form of single board computers (SBCs) which can be conveniently mounted and interconnected. Particularly popular SBCs in widespread use at the present time utilize PowerPC chips which support parity generation and checking on the data bus and Motorola MPC106 Memory controllers which support error correction codes (ECC) but does not include hardware support for forcing errors into memory for testing the ECC logic.
Such single board computers commonly include a large amount of memory which is built using very dense memory parts. High density memory parts are prone to produce single bit errors in data or instruction codes stored therein (e.g. due to impingement of alpha particles causing discharge of stored charge, particularly in high altitude applications). Single bit errors can be corrected using error correcting codes (ECC) rather than standard parity checking which is commonly provided in the processor. It is common at the present time to provide some form of error correcting code feature having at least the capability of correcting single bit errors and detecting (but not correcting) two-bit or multiple bit errors in memory controller integrated circuit chips.
It is common practice to provide for reset of a computer when power is applied to it in order to at least determine that the processor and memory are functional prior to attempting to process data therewith. As part of the "power up reset" operation, the single board computers are required to run a minimum set of built-in tests (BITs), one of which verifies that memory is operational and accessible by the processor. A reset operation which includes a similar minimum set of BITs including memory testing may also be provided when errors are detected in the course of memory accesses or in processing.
There are two basic approaches to performing a built-in test of memory: the pattern test method and the force error method. However, each of these approaches, while effective, has some characteristic drawbacks. The pattern test method is extremely time consuming since it requires the writing of a pattern into each memory location from which the pattern is read back. The force error method requires additional hardware that can force specific error correcting code patterns into memory. Such additional hardware is not generally provided in memory controllers, as indicated above, and must, at the present state of the art, be separately provided by additional hardware logic circuits and connections in the computer. In single board computers, board space (and often weight and power consumption specifications) is at such a premium that separate provision of hardware support for force error testing is impractical and possibly prohibitive in some applications. U.S. Pat. No. 5,502,732, to Arroyo et al. is exemplary of systems in which hardware support is required for ECC logic testing.
However, in systems in which SBCs are often employed, such as for providing real time control, the time required for the alternative pattern test method of memory testing is generally not acceptable. For example, upon a momentary power interruption in an aircraft, control by the SBC would not be available while the pattern test was being carried out and could precipitate a malfunction or the development of conditions from which recovery might not be possible. Many applications will also have power up time specifications which cannot be met if the pattern test method is employed to verify memory function.